The present invention relates to integrated circuits, and more particularly to an alignment mark suitable for aligning FeRAM capacitors to underlying contacts.
The semiconductor industry has long faced a demand for small, portable personal devices. These devices include cellular phones, personal computing equipment, and personal sound systems, which are sought in continuously smaller sizes and with continuously lower power requirements. At the same time that smaller and more portable personal devices are sought, computational power and on-chip memory requirements have increased. In light of these requirements, there has been a long-felt need for computational devices that have substantial memory and logic functions integrated within individual semiconductor chips. Preferably, the memory is configured such that if power is interrupted, as when a battery fails, the contents of the memory are retained. Memory that retains its content without a continuous supply of power is called non-volatile memory. Conventional non-volatile memory types include electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Ferroelectric random access memory (FeRAM) is a type of non-volatile memory that stores data in memory cells that include capacitors with ferroelectric cores. A ferroelectric core contains a ferroelectric material, such as SBT or PZT, as the dielectric. The non-volatility of FeRAM results from the bi-stable characteristic of ferroelectric materials.
There are single and dual capacitor ferroelectric memory cells. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area and thereby increases the potential density of the memory array, but is less immune to noise and process variations. A 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area and stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than the 1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 100 includes a transistor 110 and a ferroelectric storage capacitor 120. The transistor 110 includes a gate 112, a source 114, and a drain 116. The storage capacitor 120 includes a bottom electrode 122, a top electrode 124, and a ferroelectric core. The drain 116 of the transistor 110 is connected to the bottom electrode 122 of the capacitor 120. The source 114 of the transistor 110 is connected to a bit line 132 (BL). The 1T/1C cell 100 is read by applying a signal to the gate 112 through a word line 130 (WL), switching on the transistor 110. This brings the bottom electrode 122 of the capacitor 120 into communication with the bit line 132. Then, though a drive line 134 (DL), a pulse signal is applied to the top electrode 124 of the capacitor 120. The potential on the bit line 132 becomes the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric core, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 132 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read.
Prior art FIG. 2 illustrates a 2T/2C memory cell 200. The memory cell 200 comprises two transistors 202 and 204 and two ferroelectric capacitors 206 and 208, respectively. The first transistor 202 couples between a bit line 210 and the capacitor 206. The second transistor 204 couples between a bit line-bar 212 and the second capacitor 208. The capacitors 206 and 208 are connected to a common drive line 214 (DL), to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 202 and 204 of the dual capacitor ferroelectric memory cell 200 are enabled via a word line 216 (WL) to couple the capacitors 206 and 208 to the complementary logic levels on the bit line 210 and the bit-line bar 212. The common drive line 214 of the capacitors is pulsed during the write operation to polarize the dual capacitor memory cell 200 to one of two logic states.
In a read operation, the first and second transistors 202 and 204 are enabled via the word line 216 to couple the information stored on the first and second capacitors 206 and 208 to the bit line 210 and the bit line-bar line 212, respectively. A differential signal (not shown) is thus generated across the bit line 210 and the bit line-bar line 212. A sense amplifier (not shown) senses the differential signal and determines the logic level stored in memory.
Forming devices with FeRAM presents several challenges. One such challenge relates to lithographically-patterning the capacitors. Lithography refers to processes for pattern transfer between various media. In lithography for integrated circuit fabrication, the substrate is coated uniformly with a radiation-sensitive film, the resist. The film is selectively exposed with radiation (such as visible light, ultraviolet light, x-rays, or an electron beam) through an intervening master template, the mask or reticle, forming a particular pattern. Exposed areas of the coating become either more or less soluble than the unexposed areas, depending on the type of coating, in a particular solvent developer. The more soluble areas are removed with the developer in a developing step. The less soluble areas remain on the substrate, forming a patterned coating. The pattern of the coating corresponds to the image, or negative image, of the reticle. The patterned coating is used in further processing of the substrate.
When lithographically patterning a capacitor stack for a FeRAM, a challenge arises in aligning the capacitors to contacts with the underlying transistors. Aligning the capacitors generally requires alignment marks on the substrate that can be detected by a lithography tool after deposition of a capacitor stack and resist coating.
Previously, attempts were made to form an alignment mark in the contact layer that is located beneath the capacitor stack. A contact layer includes a dielectric and metal-filled vias forming the contacts. The contact layer tends to obscure detection of alignment marks formed in underlying layers, thus it was natural to try forming new alignment marks when patterning the contact layer in order to facilitate further processing.
When an alignment mark was formed in a tungsten-containing contact layer for FeRAM, it was found to be unreliable due to oxidation. Oxidation occurred while depositing a ferroelectric core, such as a PZT core, which is formed under oxidizing conditions at a temperature of about 600xc2x0 C. A diffusion barrier layer was present, but was not consistently effective in protecting the alignment marks. Oxidation distorted the alignment marks and interfered with their function, causing misalignment of the capacitors with respect to the underlying contacts.
A solution to this problem is to mask off the contacts and etch the tungsten from the alignment marks prior to forming the capacitor stack. This solution is effective, but adds to the number of lithographic steps in a process for manufacturing an integrated circuit having FeRAM. The number of lithographic steps required to form an integrated circuit generally has a significant impact on the cost of that circuit. There has long been a demand for integrated circuits and integrated circuit manufacturing processes that require fewer lithographic steps.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. A further advantage is that groups of small filled trenches tend to present a shallower topographic variation than a single large trench, and thereby better resist dust particle contamination.
Another aspect of the invention relates to an alignment mark and process wherein the alignment mark is formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.